Field-Effect Transistors (Art of Electronics, Ch. 3)

76 flashcards by Chris R.

What is a field-effect transistor (FET), in one sentence, and how does it differ fundamentally from a BJT?
What are a FET's three terminals called?
What does "transconductance device" mean, and how does it describe FETs?
What's the difference between n-channel and p-channel FETs?
What's the difference between enhancement-mode and depletion-mode FETs?
What is threshold voltage (Vth, or VGS(off) for depletion devices)?
Why can't a JFET be enhancement-mode?
What are the two operating regions of a FET, and what distinguishes each?
What is the FET "square law" for drain current in saturation?
Why do FETs behave like a BJT (exponentially) at very low (subthreshold) drain currents?
Big picture: when are FETs the right choice, and where do they fall short compared to BJTs?
Simplest JFET current source: how does it work, and what's its major weakness?
Why is a JFET's IDSS a poor parameter to design around?
How does a self-biasing source resistor improve a JFET current source?
How does a cascode JFET current source improve on a simple one, and why?
Common-source JFET amplifier voltage gain formula?
What is the "gos effect," and what's the fix for its gain-limiting impact?
How does source degeneration in a JFET common-source amplifier parallel emitter degeneration in a BJT?
What's a "series feedback" JFET–BJT hybrid amplifier, and why combine the two device types?
Why is JFET transconductance more predictable versus drain current than versus gate voltage?
What is a JFET/MOSFET source follower, and how does it parallel a BJT emitter follower?
Source follower output impedance formula?
Why is a FET follower's voltage gain typically farther from unity than a BJT emitter follower's?
Why doesn't a FET follower have a fixed, predictable DC offset the way a BJT follower's ~0.6V VBE gives?
How do you find a source follower's DC operating point graphically ("load line" method)?
How does an active current-sink pulldown improve a source follower over a plain resistor?
How does a cascode transistor improve a source follower's linearity and bandwidth?
Why does a FET-BJT "transconductance enhancer" help a follower drive a low-impedance load?
How does a FET behave as a voltage-controlled resistor, and under what condition?
rDS formula for a FET used as a variable resistor?
What causes nonlinearity in a FET-as-resistor, and what's the simple linearizing trick?
Name a practical application of a FET used as a variable resistor.
How does FET gate leakage behave with temperature, compared to a BJT's base current?
What is JFET "impact-ionization" gate current?
What is dynamic gate current, and why does it matter despite negligible DC gate current?
Why can FETs still badly attenuate high-frequency, high-source-impedance signals despite negligible DC input current?
Why is Miller-effect feedback capacitance especially troublesome in FET common-source amplifiers?
What makes MOSFETs well suited as analog (linear) switches?
Basic n-channel MOSFET analog switch: what limits the signal range it can pass?
What is a CMOS analog switch (transmission gate), and why use complementary FETs in parallel?
What's the advantage of a JFET analog switch's RON over a CMOS switch's, across signal voltage?
What is an analog multiplexer (MUX), and how does it relate to a demultiplexer?
What is "SCR latchup," and why must analog switch inputs never be driven beyond the supply rails by more than a diode drop?
Why does a CMOS switch's RON tend to rise near the midpoint between the supply rails?
What's the tradeoff between RON and parasitic capacitance/charge injection in choosing an analog switch?
What is "charge injection," and what two techniques reduce its visible effect?
Why does putting a switch inside an op-amp's feedback loop eliminate the effect of its RON?
What is a T-switch configuration, and why does it improve high-frequency OFF-isolation?
How does a simple resistively-loaded MOSFET inverter work, and what's its drawback?
What is a CMOS inverter, and why does it have essentially zero static power dissipation?
How does a CMOS NAND gate work, at the switch level?
What are the two sources of dynamic power dissipation in CMOS logic?
What is "shoot-through" (crowbar) current in CMOS logic?
What two advantages does a power MOSFET have as a switch, compared to a bipolar power transistor?
Why is a power MOSFET's "infinite input impedance" misleading for switching applications?
What is gate charge (QG), and why is it a better switching-speed figure of merit than gate capacitance alone?
Why does the Miller effect create a "plateau" in the gate-charge curve during switching?
Roughly how much gate drive current can fast switching of a power MOSFET require?
What is the MOSFET body diode, and what limitation does it impose?
Why are MOSFET gates especially vulnerable to ESD damage, and what two protections are standard?
What's the recommended way to size a power MOSFET's continuous current rating realistically?
Why don't power MOSFETs suffer from "second breakdown" the way bipolar power transistors do?
What's the key RDS(ON)-vs-temperature behavior of MOSFETs, and why does it matter for paralleling?
Why do power MOSFETs (unlike BJTs) often not need ballasting resistors when paralleled as switches?
Why is paralleling MOSFETs in a linear (not switching) application riskier?
What are two fixes for current-sharing among paralleled MOSFETs in a linear application?
How can thermal runaway still occur in a MOSFET switch, despite its negative high-current drain-current tempco?
Why do lateral power MOSFETs avoid thermal runaway in linear amplifier applications, without active compensation?
Why must a push-pull output stage's quiescent-current bias network be thermally coupled to the output devices?
What is an IGBT, and what hybrid of device characteristics does it combine?
What's a key electrical difference between an IGBT and a MOSFET regarding minimum ON voltage?
When are IGBTs generally preferred over power MOSFETs?
What is a thyristor (SCR), and how does its behavior differ from a transistor's continuous control?
Circuit-lab bridge — mosfet_switch.cir lets a 3.3V logic-level GPIO pin switch a 12V load. Which two chapter-3 facts make that work?
Circuit-lab bridge — level_shifter_bss138.cir uses one n-channel MOSFET as a bidirectional level shifter with no direction/control signal. Why does that work?
Big picture: what's the practical FET-vs-BJT decision this chapter keeps coming back to?